HexoSys Group started in early 1998 as a high tech engineering services company in Dubai, United Arab Emirates. In September 2007, HexoSys launched its engineering center in Technology Park Malaysia, Kuala Lumpur, Malaysia. And as its new office expansion since June 2011, we are occupying a bigger space of 7,000 sq. ft. with more than 60 employees in Kuala Lumpur, Malaysia.
Since its inception in 1998, HexoSys has been striving to provide outstanding hardware and software design and implementation services to the high-technology community in the USA. In 2007, HexoSys Sdn Bhd (Malaysia) has been recognized as MSC status Company by the government of Malaysia.
- Design and Verification of FPGAs with Verilog/VHDL
- Optimizing FPGA code to minimize resources / maximize clock speed.
- Verification of FPGAs using ModelSim, etc.
- Debug FPGA issues on the hardware platform
- Invent, document, and implement micro-architecture and design details for new-product features.
- Physical implementation in FPGA targets for emulation; timing closure, debug
- Outstanding hands on FPGA design and development experience on either Altera or Xilinx
- Expert experience with Verilog (or possibly VHDL) RTL design and high-speed digital design methodologies.
- FPGA Code development / design experience with either Xilinx ISE Foundation or Altera Quartus II
- FPGA Verification & Debug experience using ModelSim, (Perl, Python).
- Experience in floor planning, synthesis, and placement & routing; Xilinx and Altera is ideal
- Experience with writing BFM, monitors (PCI/PCIe, USB, and DDR2/3) and test benches.
- Extensive packet processing experience as well as full-chip verification
- 3+ years experience
- Recruiter Name:Komal SrivastavaWebsite:http://www.hexosys.com/Email Id:firstname.lastname@example.org