Digital Verification Engineer
What will I be accountable for?
Definition and implementation of digital verification processes and infrastructure
Verification and planning of the soft and hard digital radio IP in a low power, mixed signal environment
Architecting the verification strategy and plans for IP
Development of test benches and infrastructure
Ensuring best practice verification practices from within ARM and the industry are adopted and implemented
Reviewing and assessing proposed design changes working with design engineers to refine future designs ensuring that they are verifiable.
A key technical contributor and verification authority within the Business Unit
Represent the verification activities of the relevant projects, both internally and externally.
Enabling our customers to achieve the highest quality, fully verified IP
Working collaboratively with the digital designers and the analogue/ RF team in a mixed signal environment
Interaction with EDA vendors to continuously improve the verification of our designs
Methodology and advanced flow development for IP verification for current and next generation designs
Promoting and demonstrating the ARM core beliefs and behaviours
What skills, experience, and qualifications do I need?
You will require a proven track record and experience of digital verification in a suitably complex verification environment. As well as being comfortable with standard directed tests, you will have utilised common digital verification techniques such as constrained-random, UVM, formal methods etc. You will be comfortable using SystemVerilog to develop verification components and be familiar with the tools and processes for developing test benches and completing all aspects of the verification process. You must be comfortable developing verification flows to make best use of EDA tools and resources available.
Education and Qualifications
Masters degree in Electrical, Electronic, Computer or Software Engineering, Applied Physics or other relevant technical disciplines
Essential Skills and Experience
Thorough knowledge of SystemVerilog for verification of complex design IP
Significant experience of architecting and implementing functional verification environments for complex IP
Significant experience developing re-usable and scalable code.
Knowledge of UVM and understanding of formal methods
Strong scripting skills (UNIX shell scripting, Python or Perl, TCL, etc.) being able to develop scripting and infrastructure to support new flows.
Ability to quickly understand and apply complex specification details
Willingness to tackle varied and complex technical challenges
Experience working and communicating with remote design centres
Strong communication skills and ability to work well as part of a team
Desirable Skills and Experience
Experience of emulation flows and FPGA
Experience and track record of formal methods
Knowledge of C/C++/SystemC
Experience of verifying low power designs in a mixed signal environment
Experience of analogue/ mixed signal verification
Experience and track record of digital design - ideally SystemC, SystemVerilog
Experience of digital implementation and DFT
A high level of pro-activity, initiative and problem solving skills
Professional and enthusiastic approach to work, with the drive and ability to schedule own workload, planning tasks effectively
Strong communications skills and experience of working with multi-site teams
Ability to effectively work alone as well as in a team
Ability to effectively lead the digital verification activities on a major project, operate as a technical authority and mentor others engineers
Ability to promote and drive verification methodologies and activities
Good analytical skills along with the ability to think outside the box
Recruiter Name: Mr. Sridhar
Company: ALTEN CALSOFT LABS (INDIA) PRIVATE LIMITED
Email : firstname.lastname@example.org