Altran ranks as the undisputed global leader in Engineering and R&D services (ER&D). The company offers clients an unmatched value proposition to address their transformation and innovation needs. Altran works alongside its clients, from initial concept through industrialization, to invent the products and services of tomorrow. For over 35 years, the company has provided expertise in Automotive, Aeronautics, Space, Defense & Naval, Rail, Infra & Transport, Energy, Industrial & Consumer, Life Sciences, Communications, Semiconductor & Electronics, Software & Internet, Finance & Public Sector. The Aricent acquisition extends this leadership to semiconductor, digital experience and design innovation. Altran generated revenues of â¬2.9 billion in 2018, with some 47,000 employees in more than 30 countries.
Location - Hudson, MA, USA
- 5-10 years of hands-on experience with DFT and test flow with commercial EDA tools (Synopsys, Mentor) for large and complex SOCs.
- Strong fundamental knowledge of DFT techniques include JTAG, ATPG, test pattern translation, yield learning, logic diagnosis, Scan compression, IEEE 1500 Std. and MBIST, LBIST.
- Experience with Synopsys DFT Complier, Tetramax and VCS is required. Experience with TestKompress, Tessent and Modus/Encounter tool suite is a plus.
- Strong programming skills in Perl/TCL/C++ and shell scripting is preferred.
- MS/BS in Electrical or Computer engineering
Roles & Responsibilities
- Implement test strategy for SoC designed in advanced process nodes.
- Perform top/block-level DFT insertion including scan compression, boundary scan, JTAG, IEEE 1500 wrapper, MBIST, LBIST, ATPG and pattern simulation.
- Verify DFT circuitry and interface with other blocks, debug timing simulation issues.
- Closely work with physical design team to generate and validate timing constraints.
- Be able to quickly understand problem statements and innovate solutions for DFT, diagnosis and yield learning.
- Be able to work under the guidance of DFT Lead/Manager