InSemi (An ISO 9001-2015 Certified Company) creates technology solutions that enable businesses and consumers to integrate their physical and digital worlds, accelerate technology adoption and simplify everyday life. We are a team of experts that specializes in electronics design and automation, platform design and embedded technologies.

Since our inception in 2013, our thrust has been on technologies that help in the enablement of Internet of Things, cloud computing and big data. Our deep experience and understanding of the electronics value chain and digital technologies enable us to create innovative products that disrupt competition.

InSemi works closely with technology companies to create products that are otherwise not commercially available. To put it simply, we work in the gaps of technologies and fill them with solutions

We have an excellent opportunity for Verification Engineer

JD 1:

•    Minimum of  10+ years verification work experience
•    Hands on project experience with leading edge verification methodologies like OVM/UVM
•    Domain experience in PCI-e Gen2/Gen3 is must
•    Worked at system level verification/validation
•    Hands on project experience in verifying projects using PCIe, Ethernet, AMBA, and DDR2/DDR3 protocols
•    Hands on project experience in coverage/assertion driven verification
•    Good knowledge of UNIX shell scripting, Perl and TCL scripting.
•    Proven experience in writing verification plans and test bench development , simulation, and debugging
•    Good analytical and problem solving skills
•    Excellent written and verbal communication in English.
•    Good communicating skill

Must Have Skills
- Good understanding on computer architecture and processor based systems verification
- Knowledge of low power functions and techniques including clock gating , Clock scaling , power gating etc.
- Prior experience with on full-chip or sub-system verification
- Excellent Debugging and Troubleshooting skills – Mandatory
- Hands-on experience in Verilog, System Verilog, C, C++ in industry standard methodology/framework.
- Knowledge of simulation tools and coverage database visualization tools
Good to Have
- Knowledge in verification Methodologies like UVM is a plus
- Prior Experience of Low Power Verification Methodology is a advantage
Soft Skills
- Highly motivated, self-starter with good interpersonal skills and a strong team player
- Excellent communication, critical thinking and problem solving skills

Exp: 8+Yrs

Job Description:
Good knowledge of verilog, system verilog and UVM
Experience in UVM based testbench development
Experience in IP level verification
Candidate should have good debugging skills
Experience in assertion and coverage based verification
Good problem solving skills
Good communication skills

If you are interested in exploring this opportunity, please share your profile to

Appreciate sharing the below details:
Current CTC (INR):
Expected CTC (INR):
Notice Period (Should not exceed 30 days):
Current Location:
Interested Location: HYD/BLR/Sweden
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